Alphabet in talks with Marvell on two new AI chips to speed up inference in Google services
Alphabet is in talks with Marvell to develop two AI chips for inference. The first is meant to speed up data transfer through a specialized memory module; the second would be an updated version of Google's TPU for interactive applications. For the company, it is a step toward running AI services more cheaply and quickly, where latency, scale and a steady response to a stream of user requests matter most.
AI-processed from 3DNews AI; edited by Hamidun News
Alphabet has opened talks with Marvell on developing two specialized AI chips for inference, the stage at which an already trained model handles real user requests. If the project goes ahead, Google will get hardware built not for lab records but for fast, high-volume responses in interactive services.
Which chips are being discussed
The talks center on two different components. The first is a memory module meant to speed up data transfer inside an AI system. For inference this is critical: even a powerful accelerator loses its value if the model hits limits in memory bandwidth, exchange latency and slow data delivery. In large language models, these bottlenecks often determine how quickly and cheaply a system can serve the daily stream of user requests.
The second component is an updated version of the TPU, Google's in-house tensor processors, aimed at interactive applications. These are scenarios where the user expects an answer immediately: search, AI assistants, text generation, interface suggestions. The choice points to a shift in priorities: value is increasingly created not when a model is trained, but when it runs continuously on millions of short requests, where stable latency, predictability and the cost of each response matter.
Why Alphabet needs Marvell
For Alphabet, a partnership with Marvell looks pragmatic. Marvell is strong in data center infrastructure and specialized chips, while Google has been developing its own TPU line for many years. Rather than doing everything in-house, Alphabet can split responsibility: keep control of the accelerator architecture and bring in a partner for the parts of the system where memory, interconnects, packaging and fast data exchange between components matter most.
The deal also has economic logic. Inference is quickly becoming one of the most expensive layers of AI infrastructure, because it runs on constant user traffic. The more closely hardware is matched to a specific type of workload, the easier it is to scale a service without costs exploding. For Google it is a chance to lower the cost of each response and gain more control over its own technology stack; for Marvell, a chance to strengthen its position in an overheated AI accelerator market.
- A dedicated memory module can reduce bottlenecks when working with large models
- An updated TPU is better suited to conversational and other interactive scenarios
- A specialized chip usually delivers more efficiency per watt and per dollar
- For Google, it is a way to strengthen control over its own AI infrastructure
- For Marvell, it is a deeper entry into the market for AI workload accelerators
Where the effect will show up
If the talks lead to actual deliveries, users will not be the first to notice; the teams responsible for Google's infrastructure will. Inference is not a one-off run of a model but continuous work under load, where the system must answer a huge number of requests in a row, quickly. In this mode, computation as such is not the only concern: predictable response time, energy efficiency and the absence of bottlenecks in data transfer between memory and the accelerator matter too.
In practice, this means finer tuning of hardware for specific products. The market is gradually moving away from the idea of a single universal chip that is equally good at every AI task. Instead, companies assemble separate combinations of components for training, inference and interactive modes. The Alphabet–Marvell talks fit this trend well: the winners will not be those who simply have more GPUs, but those who design the entire model execution chain more precisely for real workloads.
What this means
The Alphabet–Marvell talks show that the new AI race is no longer unfolding only around models, but also around specialized hardware for everyday services. Whoever can deliver a fast answer more cheaply and more reliably will gain the advantage.
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Key Questions Answered
Which chips are being discussed?
The talks center on two different components. The first is a memory module meant to speed up data transfer inside an AI system. For inference this is critical: even a powerful accelerator loses its value if the model hits limits in memory bandwidth, exchange latency and slow data delivery. In large language models, these bottlenecks often determine how quickly and cheaply a system can serve the daily stream of user requests. The second component is an updated version of the TPU, Google's in-house tensor processors, aimed at interactive applications. These are scenarios wher
Why Alphabet needs Marvell?
For Alphabet, a partnership with Marvell looks pragmatic. Marvell is strong in data center infrastructure and specialized chips, while Google has been developing its own TPU line for many years. Rather than doing everything in-house, Alphabet can split responsibility: keep control of the accelerator architecture and bring in a partner for the parts of the system where memory, interconnects, packaging and fast data exchange between components matter most. The deal also has economic logic. Inference is quickly becoming one of the most expensive layers of AI infrastructure, be
Where the effect will show up?
If the talks lead to actual deliveries, users will not be the first to notice; the teams responsible for Google's infrastructure will. Inference is not a one-off run of a model but continuous work under load, where the system must answer a huge number of requests in a row, quickly. In this mode, computation as such is not the only concern: predictable response time, energy efficiency and the absence of bottlenecks in data transfer between memory and the accelerator matter too. In practice, this means finer tuning of hardware for specific products. The market is gradually mo
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