Intel D270 offers up to 480 GB instead of HBM, while CXL pools cut TTFT to 40%

Selectel’s October server hardware roundup may look like a collection of unrelated announcements, but a common thread runs through it. The industry is trying to work around expensive, scarce HBM while figuring out where conventional processors, rather than GPUs, belong in the age of agents. If you are planning inference on your own hardware, these announcements offer a useful map of the trends shaping 2027.

Memory capacity over speed: Intel’s bet and the CXL approach

The month’s main idea is simple. For long-context inference, memory capacity often matters more than peak bandwidth. The model and KV cache simply have to fit.

Intel has built its Crescent Island accelerator, also known as the D270 GPU, around this premise. It uses LPDDR5X instead of HBM: up to 480 GB in partner versions and 160 GB on the reference card. This is a dual-slot PCIe 5.

0 x16 card with air cooling and a 350 W TDP. Intel estimates that a single card can hold a 300-billion-parameter model, while eight cards can handle models with more than a trillion parameters. Support for PyTorch, vLLM, SGLang and Triton is promised.

For comparison, AMD’s Instinct MI450X has up to 432 GB of HBM4, while NVIDIA Rubin has 288 GB. Capacity is comparable; bandwidth is not. The roundup’s author also flags a weakness: Intel has said nothing about interconnects between cards, where PCIe will become the bottleneck.

CXL approaches the same problem from another direction. Marvell has introduced the Structera X 3406 and 3506 memory expanders. The former supports up to 9 TB using older DDR4, the latter up to 6 TB using DDR5. A single controller serves up to four hosts, and built-in LZ4 compression increases effective capacity by 2–3 times, according to Marvell. For LLMs, the company promises 40–50% lower TTFT at the same context length. The idea is to turn a fleet of DDR4 servers into a shared KV cache pool.

Samsung and AMD demonstrated a similar setup using CMM-D modules with the Dynamic Capacity Device mechanism. Memory is allocated to a host on demand and returned afterward. If one model instance’s context grows, it temporarily borrows capacity from the pool. According to Samsung, TTFT falls to 38%, while goodput increases by up to 3.3 times compared with static allocation.

Agents need CPU racks

The second trend: agent workloads involve more than inference. Tool calls, code execution, sandboxes and orchestration run on CPUs. AMD has released the Helion reference design, an ORv3 rack built exclusively around EPYC Venice processors, with up to 32,768 cores in total. An option with up to 16 Instinct MI350P GPUs is available for enterprise customers. On the same day, NVIDIA submitted its MGX 1.2 specifications to OCP and outlined its own Vera CPU rack for the same workloads. The timing hardly looks coincidental: the CPU rack is becoming a standalone unit of infrastructure.

Related announcements include Microsoft Maia 300 with 288 GB of HBM4 for inference and agents; Astera Labs Orion, supporting up to 80 PCIe accelerators of any kind per rack without being tied to NVIDIA or AMD; and the Kioxia GP1 SSD, delivering more than 20 million IOPS as an intermediate tier between HBM and conventional drives.

What to do with this—and which claims to question

Almost all these products are still reference designs or samples. Intel D270 engineering samples are already with OEMs; Marvell promises samples in the first quarter of 2027, as does Astera; and Altera Agilex 27 will not arrive until the second half of 2027. There are no prices or production systems yet. Figures such as those for Chinese company Iluvatar’s Tiangai 300, claimed to be “on par with H200,” come from the company itself and affiliated laboratories—and use a chip from 2023 as the comparison point.

Practical takeaways for teams evaluating in-house inference:

• Work out your bottleneck: memory capacity (long contexts, a large KV cache) or bandwidth. The answer determines whether “slower but larger” memory will work for you.
• Do not write off older DDR4 servers: CXL could turn them into a cache pool, but wait for independent measurements.
• Build a dedicated CPU tier for tools and sandboxes into your agent architecture, alongside GPUs.
• Check vLLM and SGLang support before buying. Press-release promises are no substitute for working kernels.

The main takeaway: the next AI infrastructure race is about more than FLOPS. It is also about cheap gigabytes per token of context.