Servers 2027: Rubin Ultra, MI500, and Open Interconnects Break the Monopolies

2027 marks a radical overhaul of the server industry. It's not just new chips arriving — the very architecture of the rack, memory, interconnects, and power delivery is changing. The three main players — NVIDIA, AMD, and Intel — enter the year with wildly different strategies: one is doubling down on power and energy draw, another is attacking on both the AI and HPC fronts, and the third is pushing back into the race with its own manufacturing process. At the same time, open standards and new memory technologies are starting to erode the existing monopolies.

NVIDIA

Rubin Ultra: from accelerator to rack-scale supercomputer

In the second half of 2027, NVIDIA will ship Rubin Ultra in the Kyber NVL576 configuration — effectively a supercomputer in a single cabinet. The specs are staggering:

• 144 accelerators per rack, each built from four Rubin Ultra dies • 100 PFLOPS FP4 per package (compute throughput in FP4 format) • Up to 1 TB of HBM4e memory per rack • NVLink 6: 3.6 TB/s of GPU-to-GPU bandwidth per accelerator, totaling 260 TB/s across the entire rack • Power draw: ~600 kW — for comparison, a Hopper rack required just 40 kW

This jump in power consumption is forcing data centers to completely rethink electrical supply, cooling, and even facility layout. NVIDIA is cementing the concept of "The Rack Is the New GPU" — the rack now functions as the unit of compute, rather than a container for individual accelerators.

AMD: a thousand-fold leap and two processors for two jobs

AMD is advancing on multiple fronts at once. The main thrust is the Instinct MI500, the company's flagship expected in 2027, built on the CDNA 6 architecture with TSMC's 2nm process and HBM4e memory. AMD claims a thousandfold increase in AI performance compared to the 2023-era MI300X (measured in tokens per second, this spans three generations in four years). Alongside it comes the MI430X — an accelerator with native FP64 support, aimed at HPC simulations and national laboratories.

To power these accelerators, AMD is rolling out its EPYC Venice processor lineup, wrapping up in the second half of 2027:

• Venice-X (SP7): 96 cores, 1,152 MB of L3 with 3D V-Cache, boosting to 5.15 GHz — aimed at HPC simulations and in-memory databases • Verano (SB1): 72 cores, 24-channel LPDDR5X, up to 5 GHz — a host CPU for GPU-dense racks, whose main job is continuously feeding the accelerators without latency

Together they form the backbone of the Helios 500 rack with MI500 accelerators, where GPUs are linked via UALink switches. Preliminary estimates suggest a full MegaPod UAL256 configuration will span three racks: 256 GPUs and 64 Verano CPUs.

Intel Diamond Rapids: a comeback with its own process

Intel has announced Diamond Rapids (Xeon 7) on the 18A-P process, launching in the second half of 2027. The key twist: the chip is built at Intel's own foundry rather than at TSMC — a strategic move while competitors fight over limited 2nm capacity.

Diamond Rapids specs:

• 16-channel DDR5 • PCIe Generation 6 support • Up to 256+ cores

Intel is entering a market already served by the established Venice platform and the upcoming Venice-X/Verano chips — competition will be fierce.

Infrastructure overhaul: PCIe 6.0, CXL, UALink, and optics

HBM4e is becoming the standard memory across all 2027 flagships. It delivers up to 3.6 TB/s of bandwidth with 16 Gbit/s pin speeds. Samsung is shipping engineering samples, SK hynix is targeting mass production in the second half of 2027, and Micron is offering customization of the logic die for specific clients. NVIDIA uses HBM4e in Rubin Ultra, AMD in the MI500. Shortages will likely persist through 2027–2028, though all three vendors' production capacity has already been contracted.

PCIe 6.0 is moving from exotic to standard. AMD EPYC Venice gets 128 lanes of PCIe 6.0 (64 GT/s), doubling bandwidth from CPU to GPU. Intel's Diamond Rapids follows the same path. Without PCIe 6.0, feeding the new generation of GPUs at full speed simply isn't physically possible. The standard won't reach consumer platforms until 2030 — for now it's entirely server-focused.

CXL 3.0/3.1 (Memory-as-a-Service) is getting its commercial launch, backed by a real software ecosystem built on top of PCIe 6.0. The technology delivers 64 GT/s with cache-coherent memory pooling across CPUs, GPUs, and external devices. Penguin Solutions has already shipped the first production CXL server for an 11 TB KV cache, recording a 75% boost in GPU utilization and a twofold increase in inference throughput. Forecasts put the CXL market growing a thousandfold in revenue by 2028.

UALink 1.0 is an open GPU interconnect standard from a consortium of major tech companies, supporting up to 1,024 accelerators in a single pod (versus 576 for NVLink). The first real hardware will appear in late 2026, with mass deployment in 2027. Crucially, cloud providers will for the first time be able to mix GPUs from different vendors in a single cluster without sacrificing bandwidth — the first genuine threat to NVIDIA's monopoly on scale-up interconnects.

Co-Packaged Optics (CPO) places the optical engine directly on the substrate next to the switch chip, eliminating the intermediate copper segment. At 800 Gbit/s and above, this cuts per-port power consumption from 15–16 W down to 6 W. TSMC is starting CPO production in the second half of 2026. NVIDIA is moving its Spectrum-X and Quantum-X switches over to CPO. LightCounting forecasts that CPO will account for roughly 30% of all 800 Gbit/s and 1.6 Tbit/s ports by 2027.

What it means

2027 truly brings major changes to the server industry. PCIe 6.0 and CXL 3.0 are reworking memory and I/O architecture, CPO is shifting network interconnects to optics, UALink is cracking open NVLink's monopoly on cluster scale-up, and HBM4e unlocks a new class of GPU bandwidth. Data centers planning infrastructure today need to lay the groundwork for this shift now — otherwise, in 2027–2028, a full architectural overhaul will turn into a costly redesign.