CXMT Claims Progress on 4F² Memory Cell, Plans Server DRAM by End of 2026

China's CXMT (ChangXin Memory Technologies) has reported "key progress" on a DRAM cell architecture called 4F square. Samsung Electronics and SK Hynix are taking the same route. CXMT president Cao Kanyu announced this at an industry event in Shanghai over the weekend, and the company's press release says the first server product on the new structure is due before the end of 2026.

What the 4F² label means

F here stands for the minimum feature size that a process technology can produce. Memory cell area is measured in squares of that size. Most current DRAM chips use a layout of around 6F². The 4F² layout is considered the theoretical minimum for a one-transistor, one-capacitor design. The cell takes up a third less area, and on the same process node density can, at the limit, rise by roughly 1.5x.

A planar structure cannot get there. 4F² usually requires a vertical transistor, with the channel standing upright rather than lying along the wafer. This is general technical context, not a quotation from CXMT's statement. In the publicly available part of the statement, the company did not specify which variant of vertical architecture it is using.

What has been claimed and what has not

The public data is thin on specifics:

• Structure: 4F square, in which, according to the company's description, memory density grows thanks to a more compact cell.
• First product: server memory.
• Deadline: before the end of 2026.
• Not disclosed: die capacity, standard (DDR5 or otherwise), speed, power consumption, yield, production volumes.

In a corporate statement, the word "progress" can mean anything from working engineering samples to a technology proven on a pilot line. Until there is data on test batches and server partners, any figures should be treated with caution.

Why this architecture

DRAM density is running up against physics: capacitors keep getting taller and thinner, while cells shrink ever more slowly. Samsung and SK Hynix are investigating vertical transistors and 3D memory as the next step after the current planar layout. CXMT is signaling that it wants to run a parallel course rather than play catch-up.

For a Chinese manufacturer, there is also a pragmatic reason. Access to the most advanced lithography equipment is restricted by export rules. A density gain from the cell architecture yields more bits per wafer without moving to finer lithography. This is my interpretation; CXMT has not framed its logic this way. But it explains well why the company is talking about this publicly, and why now.

The server segment was not chosen at random. AI data centers consume more and more DRAM, and buyers are willing to pay for every extra gigabyte per module and for energy efficiency. Margins here are higher than in consumer memory.

What to watch next

The first signal is the timeline. If server module samples do appear before the end of 2026, CXMT will noticeably narrow the gap with the market leaders. If the date slips to 2027, the announcement will look more like a claim staked on the future.

The second signal is yield. Vertical cells are hard to manufacture, and profitability is determined not by a demo on stage but by the percentage of working dies on a wafer. The third concerns customers: announcements from Chinese server vendors and cloud providers that they have qualified the modules will show how real the product is.

For those who buy servers, simply following the news is enough for now. If CXMT enters the market with DDR5 that is competitive in price and volume, pricing pressure in China may increase. For everyone else, today's announcement is interesting mainly as a benchmark: 4F² is becoming a common goal for three major players, not the exotic pursuit of a single lab.