MemSilicon Completes Tape-Out of MountTai 2026, a 1 Gbit 1T4R RRAM Chip

On 12 October 2026, China's MemSilicon (铭芯启睿) announced that it had completed the tape-out of MountTai 2026, its first-generation RRAM chip. The chip holds 1 Gbit, or 128 MB, and its 1T4R architecture means one transistor serves four resistive cells. The company calls it the first chip in the world with this density and capacity on the 1TnR technology path. That is MemSilicon's own claim: there are no independent measurements yet.

Why RRAM shares a transistor

RRAM (resistive random-access memory) stores a bit in the resistance of a thin film: high resistance represents one state, low resistance the other. The memory is non-volatile, so data persists without power. In the classic 1T1R scheme, each cell gets its own select transistor. The problem is that the transistor often takes up more area than the cell itself, and it is the transistor that limits density.

The 1TnR approach shares one transistor among several cells. In the 1T4R variant, one selector serves four cells, so more bits fit into the same area. The price is engineering complexity. Designers have to suppress leakage currents and crosstalk between neighboring cells, tune write and read voltages carefully, and cope with resistance variation, which is already significant in RRAM. That is why the move from lab arrays to Gbit class is seen as a separate barrier, not just a matter of scaling.

What we know about the chip

The available portion of the announcement publishes only basic parameters:

• developer: MemSilicon (铭芯启睿);
• name: MountTai 2026 («泰山一号»);
• announcement date: 12 October 2026;
• architecture: 1T4R, 1TnR technology path;
• capacity: 1 Gbit (≈128 MB);
• stage: tape-out, meaning the design has been handed off for manufacturing;
• positioning: a step from early research toward Gbit-class products.

It is too early to call this a finished product. Tape-out means the design is complete and the layout has gone to the fab. Working silicon still has to be obtained, tested and brought to an acceptable yield. The announcement gives no process node, fab name, write and read speeds, endurance cycles, data retention time or power consumption. These are the figures that will determine what MountTai turns out to be in practice: an experimental sample or the basis for commercial products.

Why this matters for AI

In inference, the bottleneck is data movement, not arithmetic. Accessing external memory costs noticeably more energy than the operation on the number itself. That is why the industry is looking for dense non-volatile memory next to compute or inside it: storing weights on the die and computing in memory.

For scale: 128 MB at 4-bit quantization holds roughly 256 million parameters. That is small for large LLMs, but for compact on-device models (speech recognition, vision, small assistants) it is already an interesting order of magnitude. Chips can also be combined, and the memory retains weights without power, which matters for devices that sleep often.

What to watch next

For edge AI developers and hardware teams, the coming months are a time for observation, not planning. The deciding factor will be data from returned silicon:

• write endurance and data retention at elevated temperature;
• bit error rate and cell-to-cell variation;
• read latency and energy per bit;
• process node, compatibility with logic and the volumes available.

If the numbers hold up, 1TnR will have an argument in the debate with other types of embedded memory. If not, this will be one more result in a long line of lab demonstrations. Until measurements are published, MountTai 2026 remains a claim to a technology milestone that so far only the manufacturer has confirmed.